About Marvell
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Physical Design Group at Marvell is in the infrastructure processor business unit and is responsible for developing and delivering leading-edge, high-performance data processing silicon platforms for the Carrier, Cloud, and Automotive market segments. These silicon platforms are used in wireless infrastructure and networking equipment including servers, secure gateways, and firewall. An engineer in this team will have the opportunity to experience all different aspects of Physical Design such as timing, place and route, and script
development.
What You Can Expect
As a physical design intern, you will have the opportunity to:
Run, support, and maintain the aspects of our Global Timing and Place and Route Design Flows using industry standard EDA tools for designing the next generation Multi-Ghz high-performance processor SOC chips in leading-edge CMOS process technology.
Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks through the design flow and making sure all the blocks meet timing requirements.
Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools.
Develop and implement timing and logic ECO’s.
Interface with the RTL design team to drive design modifications to resolve congestion and timing issues.
Work with the global timing team in debugging/resolving any block level timing issues seen at full chip.
Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification.
Develop technical skills through coaching and mentoring from employees on your team and others when necessary to achieve successful project outcomes
Writing scripts in Perl, Python, and TCL to achieve productivity enhancements through automation.
What We’re Looking For
Must be currently pursuing a bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or other hardware related engineering fields with an anticipated graduation date between Winter 2025 and Spring 2026
Expected Base Pay Range (USD)
36 – 71, $ per hour.
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
For Internship roles, we are proud to offer the following benefits package during the internship – medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
